Renesas Electronics /R7FA6M1AD /SYSTEM /DPSIEGR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DPSIEGR2

7 43 0 0 00 0 0 0 0 0 0 0 0 (0)DLVD1IEG 0 (0)DLVD2IEG 0 (0)DNMIEG

DNMIEG=0, DLVD1IEG=0, DLVD2IEG=0

Description

Deep Standby Interrupt Edge Register 2

Fields

DLVD1IEG

LVD1 Edge Select

0 (0): A cancel request is generated when VCC<Vdet1 (fall) is detected

1 (1): A cancel request is generated when VCC>=Vdet1 (rise) is detected

DLVD2IEG

LVD2 Edge Select

0 (0): A cancel request is generated when VCC<Vdet2 (fall) is detected

1 (1): A cancel request is generated when VCC>=Vdet2 (rise) is detected

DNMIEG

NMI Pin Edge Select

0 (0): A cancel request is generated at a falling edge

1 (1): A cancel request is generated at a rising edge

Links

()